The picks-and-shovels of silicon. Mapped.
Every AI chip in the world flows through the same dozen companies. ASML for lithography. TSMC for manufacturing. Synopsys, Cadence and Siemens for design. We mapped who owns each layer today — and the 40+ startups credibly trying to take a piece of it. Companion to the Physical AI Capital Flow Map.
How a chip actually gets made.
It starts as sand and ends as a die packaged with billions of transistors. There are six physical steps and one parallel software pipeline. Each step has one or two dominant incumbents. Each is being challenged.
Two layers drive everything. ASML in lithography. TSMC in manufacturing. The other layers have at least two viable competitors. The startup map mirrors that: most challengers cluster around the chokepoints (Substrate and xLight on ASML, Atomic Semi on TSMC at small scale) or attack the EDA software layer, where AI-native design tools can finally close a 30-year-old monopoly.
Materials, wafers, and the real chokepoint.
Three upstream layers. Two are quietly competitive duopolies. The third is ASML — a single Dutch company every fab on earth depends on. Two well-funded startups are now trying to do something about it.
Raw Materials
L1 · sand → polysiliconIncumbents
Quartz sand gets purified into 99.9999999% pure polysilicon, then grown into single-crystal ingots. Two companies dominate, mostly because nobody else wants to operate billion-dollar chemical plants that need decade-long contracts to amortize.
Challengers
Highland Materials (TN) — first new commercial US polysilicon greenfield since the IRA. $255.6M Section 48C tax credit, ~$1B total project cost, 16,000 MT/year initial capacity targeted for late-2027 operation. Industrial play, not venture-backed.
Wafers
L2 · silicon, GaN, diamondIncumbents
Two Japanese companies make the silicon discs every chip is etched onto. For specialty wafers (SiC, GaN, diamond), the field opens up.
Challengers
Vertical Semiconductor — MIT spinout (Tomás Palacios) making vertical GaN FinFETs on 200mm engineered wafers for AI data center power delivery. $11M seed Oct 2025, Playground Global led, Shin-Etsu participated (a notable signal from the incumbent).
Diamond Foundry — single-crystal CVD diamond substrates; ~$315M total raised, EU-funded €675M plant in Spain. Demonstrated 100mm monocrystalline diamond wafer in 2023.
Lithography
L3 · EUV — the bottleneckIncumbent
ASML makes the only machines on earth capable of printing features small enough for modern chips. A single High-NA EUV machine costs $380M. Every advanced fab buys from them. There is no second source.
Challengers
Substrate — James Proud's SF company; $100M at $1B led by Founders Fund (with General Catalyst, In-Q-Tel). X-ray lithography from custom particle accelerators. Claims 12nm contact arrays demonstrated. First fab targeted 2028. Public skepticism about founder pedigree is real — price accordingly.
xLight — Free-electron-laser EUV source. $40M Series B (Playground) plus $150M CHIPS Act LOI signed Dec 2025 — first Trump-era CRDO award. Pat Gelsinger is executive chairman. CEO Nicholas Kelez is ex-chief engineer of SLAC's LCLS. Lower beta than Substrate; longer timeline.
Canon NIL — Nanoimprint lithography (not a startup, but the only credible non-EUV alternative shipping today). 14nm minimum linewidth.
ASML is the highest-stakes target on the entire stack and the lowest-probability one to crack. The physics work in three or four credible directions (X-ray, FEL-EUV, nanoimprint, maskless e-beam), but the gap between a working demo and a production tool is measured in decades and tens of billions of dollars. The right exposure is one or two positions sized as moonshots, underwritten the way you'd underwrite fusion. xLight is the lower-risk version of this bet; Substrate is the higher-variance one.
The tools, the inspectors, and the place where it all happens.
Below ASML in the stack are the equipment makers that handle every other physical step — deposition, etch, inspection — and above them are the foundries that put it all together. Most equipment vendors compete in three-horse races. The fabs are a near-monopoly held by TSMC.
Deposition & Etch
L4 · doping, layers, interconnectsIncumbents
Three companies make 80% of the tools that lay down metal layers, etch patterns, and dope silicon. Healthy three-way competition keeps prices roughly honest.
Challengers
AlixLabs (Sweden) — Atomic Layer Etching Pitch Splitting. €15M Series A. MoU with VDL ETG for industrialization. Lets fabs hit advanced nodes without exclusive reliance on EUV.
Atomic Semi — Sam Zeloof + Jim Keller, ~60 engineers in SF building small, fast fabs and the tools inside them. OpenAI Startup Fund led a ~$15M seed at $100M valuation. Berkeley BWRC talk Nov 2025 signals they're emerging from stealth.
Inspection & Test
L5 · defect detectionIncumbent
KLA owns wafer inspection. Lasertec owns EUV mask inspection. Both are near-monopolies in their slices.
Challengers
Nearfield Instruments (NL) — non-destructive 3D AFM metrology. €135M Series C led by Walden Catalyst + Temasek. In HVM at a top-5 fab.
SixSense (SG) — AI software overlay on existing AOI hardware. $8.5M Series A. Deployed at GlobalFoundries and JCET. Customer-reported 30% cycle time improvement.
EuQlid — quantum diamond magnetometry for current-flow mapping inside CPUs/GPUs/HBM. Emerged Q4 2025.
Fab / Tape Out
L6 · manufacturing at scaleIncumbents
TSMC manufactures everything at the leading edge. Samsung is a credible second on certain nodes. Intel is rebuilding. If TSMC stops, the AI industry stops.
Challengers
Atomic Semi — small-fab-as-a-service. The bet is that the future has many smaller specialized fabs, not three giant ones. Currently the only startup credibly working on the fab problem, and only at sub-300mm scale.
Novel compute substrates sit alongside the fab layer, not inside it.
These four are chip companies, not foundry challengers. They design photonic, quantum-photonic, optical-I/O, or superconducting chips and have them manufactured by GlobalFoundries, TSMC, or others. They belong on the map because anyone studying silicon will ask where they fit — but they're customers of the fab layer, not competitors to it. (Cross-listed on the Physical AI Capital Flow Map under the broader compute thesis.)
PsiQuantum — photonic quantum chips manufactured at GlobalFoundries Fab 8 (Malta, NY). $1B Series E at $7B (Sep 2025). Customer of the fab layer.
Lightmatter — photonic compute (Envise) and 3D photonic interposer (Passage L200, 200+ Tbps). ~$822M raised, $4.4B valuation. Fabless. Manufacturing at GlobalFoundries.
Ayar Labs — optical I/O chiplets (TeraPHY, SuperNova). ~$500M raised. Fabless. The packaging story for GPU clusters with more I/O than copper can support.
Snowcap Compute — superconducting digital compute (Josephson junctions at 4.5K, niobium titanium nitride on 300mm). $23M seed Jun 2025, Playground Global led. Pat Gelsinger as board chair. First chip end of 2026.
The fab layer is structurally the hardest to disrupt and the most capital-intensive to attempt. We don't expect a credible TSMC challenger to emerge at the leading edge in the next decade — Atomic Semi at sub-300mm scale is as close as it gets, and that's a different market.
The more investable thesis sits one layer up: Lightmatter and Ayar Labs are moving the unit of computation from the chip to the package. If "the chip" becomes "the interposer," advanced packaging — CoWoS, photonic, optical I/O — becomes the new bottleneck, and the picks-and-shovels opportunity moves with it. These are adjacent bets, not stack-layer bets, but they're some of the most interesting ones we're tracking.
The most fundable layer is software.
Before any chip gets manufactured, it gets designed in software. Three companies — Synopsys, Cadence, Siemens — hold ~75% of that market. Their tools are 30 years old and run on Linux machines that smell faintly of the 1990s. This is the layer where AI is most likely to draw blood, and where 2026 funding has been most aggressive.
Foundation-model AI for chip design
RTL · Synthesis · Place & RouteIncumbents
The Big Three. ~75% market share. All three have launched in-house AI products (Synopsys.ai, Cadence Cerebrus, Calibre.AI) but their architecture is bolt-on, not native.
Challengers
Ricursive Intelligence — co-founded by Anna Goldie and Azalia Mirhoseini, the AlphaChip authors. $300M Series A at $4B post-money, Lightspeed led, with Sequoia, DST, NVentures. $335M total. Highest-priced startup in the entire EDA-disruptor cohort.
Cognichip — $93M total ($60M Series A Apr 2026, $33M seed May 2025). Lip-Bu Tan on the board. Physics-informed foundation model branded ACI®. 30+ semiconductor customers engaged, claims ~75% cost reduction in chip development.
Agentic verification
verification · simulation · formalIncumbents
Verification is the most expensive and time-consuming part of chip design. Often 70% of total engineering hours. Ripe for automation.
Challengers
ChipAgents — UCSB professor William Wang, founded June 2024. $74M total ($50M Series A1 led by Matter Venture Partners, TSMC-backed). 140x YoY ARR growth, deployed at 80 semiconductor companies. Advisory board includes ex-CEOs of Mentor, Cadence, and the former Synopsys CTO.
ChipStack — acquired by Cadence in November 2025, relaunched as the "Cadence ChipStack AI Super Agent." The canary. More acquisitions coming.
Analog, PCB & IP Cores
layout · routing · coresIncumbents
Virtuoso has owned analog layout for 30 years with effectively no competition. Arm has owned mobile cores for nearly as long.
Challengers
Quilter — physics-driven RL for PCB layout. $40M raised (Benchmark + Index). "Project Speedrun" booted an 843-component Linux computer on first try after one week of AI-driven design.
Astrus (Toronto) — AlphaZero-style RL for analog SerDes layout. $8M USD seed led by Khosla. Founders trained by an AlphaGo advisor.
Tenstorrent — Jim Keller. Raising at a reported $3.2B pre-money (Fidelity-led, per The Information Nov 2025). RISC-V CPU IP with full RTL source-code access — a direct Arm challenge.
This is the most fundable layer of the entire stack, and also the layer where the consolidation clock is loudest. Cadence acquiring ChipStack at ~20 people validates the thesis and tells you the next dozen single-feature AI-verification copilots are exit targets, not platforms. The remaining standalone bets need to be platform-scale (Ricursive, Cognichip) or category-defining in a category the Big Three don't yet own (Quilter for PCB, Tenstorrent for IP).
The names worth tracking, sorted by conviction.
Three tiers. The first is the highest-conviction picks-and-shovels positions, sized like normal venture bets. The second is capital-heavy moonshots that need staged diligence. The third is the watch list.
Software speed of light
- Ricursive Intelligence — AlphaChip team, $4B mark, hard to access.
- Cognichip — credible alternative at a fraction of the price. Lip-Bu Tan on board.
- ChipAgents — clearest revenue traction in agentic verification.
- Quilter — Tony Fadell signal, Benchmark/Index/Coatue stack. Shipped real hardware.
Underwrite like deep tech
- Substrate — X-ray litho. High beta. Diligence the team beyond Proud.
- xLight — FEL-EUV source. Lower beta. Long hold (10 years).
- Atomic Semi — Zeloof + Keller. Wait for first paying fab customer.
- Vertical Semi — MIT GaN-on-Si. Shin-Etsu validation at seed.
Earlier, narrower, or both
- Astrus — analog layout RL.
- Diode Computers — PCB-as-code.
- Nearfield Instruments — late-stage metrology.
- Snowcap Compute — superconducting compute.
- Tenstorrent — Arm-IP disruption pure-play.
- PsiQuantum — secondary access if available.
Benchmarks that would change the thesis
- Synopsys or Siemens acquires ChipAgents, Silimate, or another verification copilot in 2026 → category enters consolidation phase; only platform-scale plays survive.
- First full-stack chip tape-out designed end-to-end by Ricursive or Cognichip → re-rates the entire AI-EDA category upward.
- Substrate demonstrates a third-party-verified sub-10nm working die from X-ray lithography → moves from speculative to Tier 1.
- xLight CHIPS LOI converts to binding award, OR a scanner OEM agrees to integrate the FEL source → de-risks materially.
- Atomic Semi announces a named paying fab customer beyond itself → unblocks the commercial thesis.
How this was built, and where the data is weakest.
Sources & approach
- SourcesPrimary company filings and press releases, Crunchbase, PitchBook Premium, Sequoia podcast appearances, EE Times, Business Wire, Tom's Hardware, Semiconductor Engineering, NIST and Department of Commerce announcements, founder X posts.
- Window2023 through Q2 2026. Funding rounds are version-stamped at last public close.
- CoverageSeven stack layers (six physical + EDA software). 40+ challenger companies surfaced. Not exhaustive — stealth companies are by definition absent.
- RefreshQuarterly with running corrections. Subscribe for the next update.
Known caveats
- SpellingThe AI-EDA company is Ricursive Intelligence, not "Recursive." The lithography company is Substrate (James Proud's SF company), distinct from any other entity by that name.
- SubstrateTechnical claims (12nm contact arrays, $10K-per-wafer) come from the company itself. Independent analysts (Fox Chapel Research, summarized in Tom's Hardware) have publicly questioned founder pedigree and the credibility of the demonstrations. Treat accordingly.
- Atomic SemiValuation ($100M) and seed size (~$15M) come from a January 2023 TechCrunch report citing unnamed sources. The 60-engineer team count is current as of Nov 2025 (Berkeley BWRC). A follow-on round has likely closed but is not public.
- TenstorrentThe reported $3.2B pre-money Fidelity round comes from The Information citing two people with knowledge of the talks. Confirm terms directly before underwriting.
- AI claims"Designless," "recursive self-improvement," and "AI-native" are forward-looking marketing across the EDA-disruptor cohort. Real demonstrations to date are narrow proofs of concept, not full-SoC frontier-node tape-outs. Spot one missing? Tell us.
Built by Anand Iyer at Canonical · v0.1 · Educational tool. Not investment advice. Data is point-in-time and not exhaustive.